
`include "common_header.verilog"

//  *************************************************************************
//  File : top_40g_contc_xlgmii
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited.
//  Copyright (c) 2014 MorethanIP
//  Muenchner Strasse 199, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  http://www.morethanip.com
//  *************************************************************************
//  Designed by : Muhammad Anisur Rahman, Thomas Schrobenhauser
//  info@morethanip.com
//  *************************************************************************
//  Description : 40G MAC with Reconciliation Sub-Layer
//  Version     : $Id: top_40g_contc_xlgmii.v,v 1.20 2017/05/29 15:15:19 gc Exp $
//  *************************************************************************

module top_40g_contc_xlgmii (
   reset_rxclk,
   reset_txclk,
   xlgmii_rxclk,
   xlgmii_rxclk_ena,
   xlgmii_rxc,
   xlgmii_rxd,
   xlgmii_rxt0_next,
   xlgmii_txclk,
   xlgmii_txclk_ena,
   xlgmii_txc,
   xlgmii_txd,
   reg_lowp,
   reg_lowp_ena,
   lowp_ena,
   lpi_txhold,
   lf_state,
   rf_state,
   li_state,
   tx_loc_fault,
   tx_rem_fault,
   tx_li_fault,
   rx_data_int,
   rx_sop_int,
   rx_eop_int,
   rx_wren_int,
   rx_dval_int,
   rx_a_full,
   rx_stat_data,
   rx_stat_wren,
   rx_preamble,
   tx_stat_empty,
   tx_stat,
   tx_data_err_int,
   tx_data_int,
   tx_sop_int,
   tx_eop_int,
   tx_sav_int,
   tx_rden_int,
   tx_rden_int_sop,
   tx_isidle,
   tx_empty,
   tx_underflow,
   tx_preamble,
`ifdef MTIPMAC_1SIF
   os_tx_err,
`endif
   rx_sfd_o,
   tx_sfd_o,
   xgmii_rx_sop_shift,
   xgmii_tx_sop_shift,
   frc_in_tx,
   tx_stat_id,
   tx_stat_ts_frm,
   tx_stat_pgen,
   tx_ts_val_int,
   tx_ts_int,
   tx_ts_id_int,
   tx_ts_frm_out,
   pause_fwd,
   mac_addr,
   tx_enable,
   tx_pad_in,
   tx_ipg_comp_cnt,
   rx_enable,
   frm_lgth_max,
   sfd_any,
   tx_flush,
   pfc_mode,
   force_send_idle,
   disable_flt_hdl,
   xgmii_mode,
`ifdef MTIPM64B_SHORT_IPG
   short_ipg,
`endif      
`ifdef MTIPM10_MAGIC_ENA
   magic_ena,
   magic_ind,
`endif
   rsv_stat_val,
   rsv_stat,
   rsv_stat_pfc,
   frm_align_err,
   tsv_stat_val,
   tsv_stat,
   tsv_stat_pfc
   );

parameter       RX_STAT_DAT_WIDTH_64 = 25;
`include "mtip_40geth_pack_package.verilog"


input   reset_rxclk;            //  Active High reset for xlgmii_rxclk domain
input   reset_txclk;            //  Active High reset for xlgmii_txclk domain
input   xlgmii_rxclk;           //  XLGMII receive clock
input   xlgmii_rxclk_ena;       //  XLGMII receive clock enable
input   [7:0] xlgmii_rxc;       //  XLGMII receive control
input   [63:0] xlgmii_rxd;      //  XLGMII receive data
input   xlgmii_rxt0_next;       //  XLGMII terminate on lane 0 in next word
input   xlgmii_txclk;           //  XLGMII transmit clock
input   xlgmii_txclk_ena;       //  XLGMII transmit clock enable
output  [7:0] xlgmii_txc;       //  XLGMII transmit control
output  [63:0] xlgmii_txd;      //  XLGMII transmit data
output  reg_lowp;               //  Low Power Indication
input   reg_lowp_ena;           //  Low Power Generation - pin
input   lowp_ena;               //  Low Power Generation - register bit
input   lpi_txhold;             //  Request MAC to hold transmit (not serving FIFO, transmit idle)
output  lf_state;               //  Local Fault Indication
output  rf_state;               //  Remote Fault Indication
output  li_state;               //  RX receives LinkInterruption sequences
input   tx_loc_fault;           //  Force RS TX to send LF sequences
input   tx_rem_fault;           //  Force RS TX to send RF sequences
input   tx_li_fault;            //  Force RS TX to send LinkInterruption sequences
output  [63:0] rx_data_int;     //  Receive Data to FIFO
output  rx_sop_int;             //  Receive Start of Packet
output  rx_eop_int;             //  Receive End of Packet
output  rx_wren_int;            //  Receive Data FIFO write enable
output  rx_dval_int;                    //  Receive Data valid
input   rx_a_full;              //  Receive Data FIFO almost full
output  [3 + RX_STAT_DAT_WIDTH_64-1:0] rx_stat_data;         //  Receive Frame Status & Error indications
output  rx_stat_wren;           //  Receive Status FIFO write enable
output  [55:0] rx_preamble;     //  Receive frame preamble (stable from sop)
input   tx_stat_empty;          //  Transmit Status FIFO Word Empty
input   [4:0] tx_stat;          //  Transmit Status Word
input   tx_data_err_int;        //  Memory read error, need to corrupt frame
input   [63:0] tx_data_int;     //  Transmit Data from FIFO
input   tx_sop_int;             //  Transmit Start of Packet
input   tx_eop_int;             //  Transmit End of Packet
input   tx_sav_int;             //  Transmit Data Section Available in FIFO
output  tx_rden_int;            //  Transmit Data FIFO Read tx_enable
output  tx_rden_int_sop;        //  Transmit reads first word from FIFO
output  tx_isidle;              //  Transmit Statemachine is in IDLE
input   tx_empty;               //  Transmit Data FIFO Empty
output  tx_underflow;           //  Transmit Underflow
input   [55:0] tx_preamble;     //  Transmit frame preamble (sampled at sop)
`ifdef MTIPMAC_1SIF
output  os_tx_err;              //  Transmit frame error
`endif
output  rx_sfd_o;               //  SFD detected in RX (rxclk)
output  tx_sfd_o;               //  SFD transmitted (txclk)
output  xgmii_rx_sop_shift;     //  XGMII 4-Byte Column Shift of SOP     
output  xgmii_tx_sop_shift;     //  XGMII 4-Byte Column Shift of SOP     
input   [TS_WIDTH-1:0] frc_in_tx;       //  captured time synchronous to tx clock domain
input   [TSID_WIDTH-1:0] tx_stat_id;    //  frame identifier
input   tx_stat_ts_frm;         //  store timestamp command to tx
input   tx_stat_pgen;           //  Internally generated pause frame
output  tx_ts_val_int;          //  tx_ts_xxx valid indication
output  [TS_WIDTH-1:0] tx_ts_int;       //  transmit timestamp
output  [TSID_WIDTH-1:0] tx_ts_id_int;  //  frame identifier
output  tx_ts_frm_out;          //  Transmit Timestamp Frame
input   pause_fwd;              //  Forward Pause Frames to Application
input   [47:0] mac_addr;        //  Device Ethernet MAC address
input   tx_enable;              //  Enable / Disable MAC transmit path
input   tx_pad_in;              //  Transmit Padding Enable
input   [15:0] tx_ipg_comp_cnt; //  IPG compensation count
input   rx_enable;              //  Enable / Disable MAC receive path
input   [15:0] frm_lgth_max;    //  Maximum Frame Length
input   sfd_any;                //  allow any SFD character
input   tx_flush;               //  Flush egress pipeline
input   pfc_mode;               //  PFC mode(1) or Link Pause mode (0)
input   force_send_idle;        //  force Idle send
input   disable_flt_hdl;        //  if '1', RX RS does not affect TX data path
input   xgmii_mode;             //  XGMII mode enable (0=XLGMII, 1=XGMII)
`ifdef MTIPM64B_SHORT_IPG
input   short_ipg;              //  if 1, short IPG used
`endif 
`ifdef MTIPM10_MAGIC_ENA
input   magic_ena;              //  enable magic packet detection (drop all others)
output  magic_ind;              //  magic packet detected indication
`endif
output  rsv_stat_val;           //  Receive Statistic Vector Valid.
output  [31:0] rsv_stat;        //  Receive Statistic Vector.
output  [7:0] rsv_stat_pfc;     //  pfc class bits from received PFC frame
output  frm_align_err;          //  Received Frame Aligment Error Indication
output  tsv_stat_val;           //  Transmit Statistic Vector Valid.
output  [24:0] tsv_stat;        //  Transmit Statistic Vector.
output  [7:0] tsv_stat_pfc;     //  the class enable of latest generated frame

wire    [7:0] xlgmii_txc;
wire    [63:0] xlgmii_txd;
wire    reg_lowp;
wire    lf_state;
wire    rf_state;
wire    li_state;
wire    [63:0] rx_data_int;
wire    rx_sop_int;
wire    rx_eop_int;
wire    rx_wren_int;
wire    rx_dval_int;
wire    [3 + RX_STAT_DAT_WIDTH_64-1:0] rx_stat_data;
wire    rx_stat_wren;
wire    [55:0] rx_preamble;
wire    tx_rden_int;
wire    tx_rden_int_sop;
wire    tx_isidle;
wire    tx_underflow;
`ifdef MTIPMAC_1SIF
wire    os_tx_err;
`endif
wire    rx_sfd_o;
wire    tx_sfd_o;
wire    xgmii_rx_sop_shift;
wire    xgmii_tx_sop_shift;
wire    tx_ts_val_int;
wire    [TS_WIDTH-1:0] tx_ts_int;
wire    [TSID_WIDTH-1:0] tx_ts_id_int;
wire    tx_ts_frm_out;
`ifdef MTIPM10_MAGIC_ENA
wire    magic_ind;
`endif
wire    rsv_stat_val;
wire    [31:0] rsv_stat;
wire    [7:0] rsv_stat_pfc;
wire    frm_align_err;
wire    tsv_stat_val;
wire    [24:0] tsv_stat;
wire    [7:0] tsv_stat_pfc;

wire    [7:0] xlgmii_rxc_int;   //  XLGMII receive control
wire    [63:0] xlgmii_rxd_int;  //  XLGMII receive data
wire    xlgmii_rxt0_next_int;   //  XLGMII terminate on lane 0 in next word
wire    [63:0] rx_d;            //  XLGMII Receive data
wire    rx_dval;                //  XLGMII Receive data valid
wire    rx_start;               //  XLGMII Start of Frame
wire    rx_end;                 //  XLGMII End of Frame
wire    [2:0] rx_final_size;    //  XLGMII Define size of final data word
wire    frame_err;              //  XLGMII Frame error received
wire    phy_err;                //  XLGMII Control code error
wire    rs_fault;               //  XLGMII Link fault sequence detected (any)
wire    tx_rsfault;             //  XLGMII Reconciliation does not serve MAC, hold it reading a new frame
wire    lf_state_int;           //  Local Fault Indication (rxclk)
wire    rf_state_int;           //  Remote Fault Indication (rxclk)
wire    li_state_int;           //  RX receives LinkInterruption sequences (rxclk)
wire    tx_val;                 //  XLGMII Transmit data valid
wire    [63:0] tx_d;            //  XLGMII Transmit data
wire    [2:0] tx_final_size;    //  XLGMII Transmit final data word size
wire    tx_err;                 //  XLGMII Transmit error
wire    tx_end;                 //  Transmit last word on tx_d (eop)
wire    tx_start;               //  transmit first word on tx_d (sop)
wire    txipg_dval;             //  transmit enable (delayed)
wire    [1:0] txipg_eop;        //  End of frame for Tx IPG calculation
wire    [2:0] txipg_mod;        //  Last word modulo, valid when txipg_eop asserts
wire    txipg_crc;              //  MAC appends CRC
wire    [1:0] txipg_sub1;       //  Idle block was removed, return to normal operation
wire    txipg_done;             //  tx ipg done, next frame can be sent
wire    [2:0] txipg_dic;        //  current DIC
wire    [1:0] txipg_norm;       //  1:normal, 0:request to remove 1 block to compensate for MLD
wire    [7:0] xlgmii_txc_int;   //  XLGMII transmit control
wire    [63:0] xlgmii_txd_int;  //  XLGMII transmit data
wire    tx_rden_int_int;        //  Transmit Data FIFO Read tx_enable
wire    rden_int_eop;           //  Transmit reads first word from FIFO
wire    tsv_stat_val_int;       //  Transmit Statistic Vector Valid.
wire    [24:0] tsv_stat_int;    //  Transmit Statistic Vector.
wire    tsv_stat_pgen;          //  Internally generated pause frame
wire    pause_fwd_r;
wire    rx_enable_r;
wire    tx_flush_r;
wire    tx_flush_t;
wire    reg_lowp_ena_t;         //  sync'ed to txclk
wire    lowp_ena_int_t;         //  sync'ed to txclk
wire    lpi_txhold_t;           //  Request MAC to hold transmit (not serving FIFO, transmit idle)
wire    lowp_ena_t;             //  final command in txclk
wire    mac_lowp_ena;           //  to MAC TX statemachine, suppress fetching of frames
wire    rs_lowp_ena;            //  to RS layer transmit LPI sequences
wire    tx_loc_fault_t;         //  Force TX LF, sync'ed
wire    tx_rem_fault_t;         //  Force TX RF, sync'ed
wire    tx_li_fault_t;          //  Force TX LI, sync'ed
wire    xgmii_mode_t;           //  XGMII mode enable (0=XLGMII, 1=XGMII)
wire    rsv_stat_val_int;       //  Receive Statistic Vector Valid.
wire    [31:0] rsv_stat_int;    //  Receive Statistic Vector
`ifdef MTIPM10_MAGIC_ENA
wire    magic_rxstop;           //  stop rx datapath writing into FIFO
`endif

// Sync to correct clock domains

mtip_xsync #(3) U_RSYNC (
          .data_in({pause_fwd, rx_enable, tx_flush}),
          .reset(reset_rxclk),
          .clk(xlgmii_rxclk),
          .data_s({pause_fwd_r, rx_enable_r, tx_flush_r}));

mtip_xsync #(5) U_TSYNC (
          .data_in({lpi_txhold, reg_lowp_ena, lowp_ena, tx_flush, xgmii_mode}),
          .reset(reset_txclk),
          .clk(xlgmii_txclk),
          .data_s({lpi_txhold_t, reg_lowp_ena_t, lowp_ena_int_t, tx_flush_t, xgmii_mode_t}));

assign lowp_ena_t = reg_lowp_ena_t | lowp_ena_int_t;

// Sync Tx fault generation command pins

mtip_xsync #(3) U_TSYNCF (
          .data_in({tx_loc_fault, tx_rem_fault, tx_li_fault}),
          .reset(reset_txclk),
          .clk(xlgmii_txclk),
          .data_s({tx_loc_fault_t, tx_rem_fault_t, tx_li_fault_t}));


//  RX SOP Alignment
//  ----------------
rx_sop_align U_RXALIGN (
          .reset(reset_rxclk),
          .clk(xlgmii_rxclk),
          .cgmii_rxclk_ena(xlgmii_rxclk_ena),
          .cgmii_rxc_in(xlgmii_rxc),
          .cgmii_rxd_in(xlgmii_rxd),
          .xlgmii_rxt0_next_in(xlgmii_rxt0_next),
          .cgmii_rxc(xlgmii_rxc_int),
          .cgmii_rxd(xlgmii_rxd_int),
          .xlgmii_rxt0_next(xlgmii_rxt0_next_int),
          .sop_shift(xgmii_rx_sop_shift)
          );


//  RS Layer
//  --------
rs_64 U_RS (
          .reset_rxclk(reset_rxclk),
          .reset_txclk(reset_txclk),
          .enable_rx(rx_enable_r),
          .xgmii_mode(xgmii_mode),
          .force_send_idle(force_send_idle),
          .disable_flt_hdl(disable_flt_hdl),
          .lowp_ena_t(rs_lowp_ena),
          .xlgmii_rxclk(xlgmii_rxclk),
          .xlgmii_rxclk_ena(xlgmii_rxclk_ena),
          .xlgmii_rxc(xlgmii_rxc_int),
          .xlgmii_rxd(xlgmii_rxd_int),
          .xlgmii_rxt0_next(xlgmii_rxt0_next_int),
          .xlgmii_txclk(xlgmii_txclk),
          .xlgmii_txclk_ena(xlgmii_txclk_ena),
          .xlgmii_txc(xlgmii_txc_int),
          .xlgmii_txd(xlgmii_txd_int),
          .rx_d(rx_d),
          .rx_dval(rx_dval),
          .rx_start(rx_start),
          .rx_end(rx_end),
          .rx_final_size(rx_final_size),
          .frame_err(frame_err),
          .phy_err(phy_err),
          .rs_fault(rs_fault),
          .tx_val(tx_val),
          .tx_d(tx_d),
          .tx_final_size(tx_final_size),
          .tx_err(tx_err),
          .tx_end(tx_end),
          .tx_rsfault(tx_rsfault),
          .lf_state(lf_state_int),
          .rf_state(rf_state_int),
          .li_state(li_state_int),
          .tx_loc_fault(tx_loc_fault_t),        // sync'ed
          .tx_rem_fault(tx_rem_fault_t),        // sync'ed
          .tx_li_fault(tx_li_fault_t),          // sync'ed
          .rs_lowp(reg_lowp)
          );

assign lf_state = lf_state_int;
assign rf_state = rf_state_int;
assign li_state = li_state_int;


//  TX XGMII Shifter
//  ----------------
mac40_tx_xgmii U_XGMII (
          .reset_txclk(reset_txclk),
          .xlgmii_txclk(xlgmii_txclk),
          .xlgmii_txclk_ena(xlgmii_txclk_ena),
          .xgmii_mode(xgmii_mode_t),
          .eop(txipg_eop[0]),
          .mod(txipg_mod),
          .crc(txipg_crc),
          .dic2(txipg_dic[2]),
          .txc_in(xlgmii_txc_int),
          .txd_in(xlgmii_txd_int),
          .txc_out(xlgmii_txc),
          .txd_out(xlgmii_txd),
          .sop_shift(xgmii_tx_sop_shift)
          );


//  TX STM IPG Control
//  ------------------
mac40_tx_ipg U_IPG (
          .reset_txclk(reset_txclk),
          .xlgmii_txclk(xlgmii_txclk),
          .xlgmii_txclk_ena(xlgmii_txclk_ena),
          .tx_enable(tx_enable),
          .xgmii_mode(xgmii_mode_t),
          .ipg_comp_cnt(tx_ipg_comp_cnt),
          .txipg_eop(txipg_eop),
          .txipg_mod(txipg_mod),
          .txipg_crc(txipg_crc),
          .txipg_sub1(txipg_sub1),
          .txipg_done(txipg_done),
          .txipg_dic(txipg_dic),
          .txipg_norm(txipg_norm)
          );

// =============================================================

//  40G MAC
//  -------
top_40g_contc 


#(
        // use instance parameters instead package parameters
          .RX_STAT_DAT_WIDTH_64(RX_STAT_DAT_WIDTH_64))     // RX Frame Status


U_MAC (
          .reset_rxclk(reset_rxclk),
          .reset_txclk(reset_txclk),
          .xlgmii_txclk(xlgmii_txclk),
          .xlgmii_txclk_ena(xlgmii_txclk_ena),
          .xlgmii_rxclk(xlgmii_rxclk),
          .rx_start(rx_start),
          .rx_end(rx_end),
          .rx_d(rx_d),
          .rx_dval(rx_dval),
          .rx_final_size(rx_final_size),
          .frame_err(frame_err),
          .phy_err(phy_err),
          .rs_fault(rs_fault),
          .rs_fault_ored(tx_rsfault),
          .tx_val(tx_val),
          .tx_d(tx_d),
          .tx_final_size(tx_final_size),
          .tx_err(tx_err),
          .tx_end(tx_end),
          .tx_start(tx_start),
          .txipg_dval(txipg_dval),
          .txipg_eop(txipg_eop),
          .txipg_mod(txipg_mod),
          .txipg_crc(txipg_crc),
          .txipg_sub1(txipg_sub1),
          .txipg_done(txipg_done),
          .txipg_dic(txipg_dic),
          .txipg_norm(txipg_norm),
          .rx_data_int(rx_data_int),
          .rx_sop_int(rx_sop_int),
          .rx_eop_int(rx_eop_int),
          .rx_wren_int(rx_wren_int),
          .rx_dval_int(rx_dval_int),
          .rx_a_full(rx_a_full),
          .rx_stat_data(rx_stat_data),
          .rx_stat_wren(rx_stat_wren),
          .rx_preamble(rx_preamble),
          .tx_stat_empty(tx_stat_empty),
          .tx_stat(tx_stat),
          .tx_stat_pgen(tx_stat_pgen),
          .tx_data_err_int(tx_data_err_int),
          .tx_data_int(tx_data_int),
          .tx_sop_int(tx_sop_int),
          .tx_eop_int(tx_eop_int),
          .tx_sav_int(tx_sav_int),
          .tx_rden_int(tx_rden_int_int),        //  local
          .tx_empty(tx_empty),
          .tx_underflow(tx_underflow),
          .tx_rden_int_sop(tx_rden_int_sop),
          .tx_isidle(tx_isidle),
          .tx_preamble(tx_preamble),
        `ifdef MTIPM10_MAGIC_ENA
          .magic_rxstop(magic_rxstop),
        `endif
        `ifdef MTIPMAC_1SIF
          .os_tx_err(os_tx_err),
        `endif
          .lowp_ena_t(mac_lowp_ena),
          .pause_fwd(pause_fwd_r),
          .mac_addr(mac_addr),
          .tx_enable(tx_enable),
          .tx_pad_in(tx_pad_in),
          .rx_enable(rx_enable),
          .frm_lgth_max(frm_lgth_max),
          .sfd_any(sfd_any),
          .tx_flush(tx_flush_t),
          .pfc_mode(pfc_mode),
`ifdef MTIPM64B_SHORT_IPG
          .short_ipg(short_ipg),
`endif

          .rsv_stat_val(rsv_stat_val_int),
          .rsv_stat(rsv_stat_int),
          .rsv_stat_pfc(rsv_stat_pfc),
          .frm_align_err(frm_align_err),
          .tsv_stat_val(tsv_stat_val_int),      //  local
          .tsv_stat(tsv_stat_int),              //  local
          .tsv_stat_pfc(tsv_stat_pfc),
          .tsv_stat_pgen(tsv_stat_pgen)
          );

assign tx_rden_int  = tx_rden_int_int;   //  route up locally tapped signals
assign tsv_stat_val = tsv_stat_val_int;
assign tsv_stat     = tsv_stat_int;
assign rsv_stat_val = rsv_stat_val_int;
assign rsv_stat     = rsv_stat_int;

// =============================================================

//  Timestamping RX
//  ---------------
assign rx_sfd_o = rx_start & rx_dval;   //  data valid

//  Timestamping TX
//  ---------------
assign tx_sfd_o = tx_start & xlgmii_txclk_ena;
assign rden_int_eop = tx_rden_int_int & tx_eop_int;   //  indicate when status data is valid

tsm40_txtsi U_TSMT (
          .reset_txclk(reset_txclk),
          .xgmii_txclk(xlgmii_txclk),
          .xgmii_txclk_ena(xlgmii_txclk_ena),
          .frc_in_tx(frc_in_tx),
          .rden_int_eop(rden_int_eop),
          .tx_stat_id(tx_stat_id),
          .tx_stat_ts_frm(tx_stat_ts_frm),
          .tsv_stat_val(tsv_stat_val_int),
          .tsv_stat_gpause(tsv_stat_pgen),            //  generated pause
          .tx_ts_val_int(tx_ts_val_int),
          .tx_ts_int(tx_ts_int),
          .tx_ts_id_int(tx_ts_id_int),
          .tx_ts_frm_out(tx_ts_frm_out)
          );

// =============================================================

//  LPI and MAC Tx stop control
//  ---------------------------
lpi_txhold_ctrl U_LPITXHOLD (
          .reset_txclk(reset_txclk),
          .tx_clk(xlgmii_txclk),
          .tx_clk_ena(xlgmii_txclk_ena),        //  true one to the MAC
          .lpi_req(lowp_ena_t),
          .lpi_txhold(lpi_txhold_t),            //  MAC status
          .tx_empty(tx_empty),
          .tx_dval(txipg_dval),                 //  registered from statemachine
          .mac_lowp_ena(mac_lowp_ena),
          .rs_lowp_ena(rs_lowp_ena)
          );

`ifdef MTIPM10_MAGIC_ENA

   magic_det_ctrl64 U_MAGICDET (

          .reset_rxclk(reset_rxclk),
          .rx_clk(xlgmii_rxclk),
          .rx_clk_ena(rx_dval),
          .mac_addr(mac_addr),
          .magic_ena(magic_ena),
          .magic_ind(magic_ind),
          .magic_rxstop(magic_rxstop),
          .rx_d(rx_d),                          // from RS
          .rsv_stat_val(rsv_stat_val_int),
          .rsv_stat_crcerr(rsv_stat_int[17])); 

`endif

endmodule // module top_40g_contc_xlgmii
